A dual-port SRAM can read and write the SRAM cell through two ports, respectively, each of the ports having a corresponding set of address bus, data bus and control signals. The two ports can read the SRAM cells of the same address simultaneously, and can also read different SRAM cells, respectively. In the two cases the read currents are different, which will be the minimal when the two ports read the SRAM cells of the same address simultaneously. As shown in FIG. 1, it is a read-write schematic diagram of an existing dual-port SRAM. A bit line BLA and a wordline WLA correspond to a first port, and a bit line BLB and a wordline WLB correspond to a second port. Vread represents the read voltage.
When the two ports read the same address simultaneously, the MOS transistors of the same address, M102a and M102b, are both opened, their read currents being half of the current of the MOS transistor M101, respectively, with the read current formula being the following formula (1). When one address is only read by one port, only one of the MOS transistors of the same address, M102a and M102b, is opened, its read current being equal to the current of the MOS transistor M101, with the read current formula being the following formula (2).
                              I                      read            ,            dual                          =                                                            K                pg                            ⁡                              (                                                      V                    DD                                    -                                      V                                          read                      ,                      dual                                                        -                                      V                    tpg                                                  )                                      2                    =                                    1              2                        ⁢                                                            K                  pd                                ⁡                                  (                                                            V                      DD                                        -                                          V                      tpd                                        -                                                                  1                        2                                            ⁢                                              V                                                  read                          ,                          dual                                                                                                      )                                            ·                              V                                  read                  ,                  dual                                                                                        (        1        )                                          I                      read            ,            single                          =                                                            K                pg                            ⁡                              (                                                      V                    DD                                    -                                      V                                          read                      ,                      single                                                        -                                      V                    tpg                                                  )                                      2                    =                                                    K                pd                            ⁡                              (                                                      V                    DD                                    -                                      V                    tpd                                    -                                                            1                      2                                        ⁢                                          V                                              read                        ,                        single                                                                                            )                                      ·                          V                              read                ,                single                                                                        (        2        )            
In the above formulas (1) and (2), the MOS transistor M101 works in a resistive region, the MOS transistors M102a or M102b work in a saturation region, Iread,dual and Vread,dual respectively represent the read current and the read voltage when the two ports read the same address simultaneously, Iread,single and Vread,single respectively represent the read current and the read voltage when only one port reads the same address, Kpg represents the coefficient of the current formula of the MOS transistor M102a or M102b, VDD represents the power supply voltage, Vtpg represents the threshold voltage of the MOS transistor M102a or M102b, Kpd represents the coefficient of the current formula of the MOS transistor M101, and Vtpd represents the threshold voltage of the MOS transistor M101.
The SRAM cell structure (cell) has three operating states, which are “Select”, “Half Select” and “Static”, respectively. The power consumption models of the three states are respectively as follows:
Select: The Bit cell discharges a bit line capacitor CBL, with the power consumption expressed by the following formula (3):PSelect=Iread·Twl·Vdd·f  (3)
In the formula (3), Pselect represents the power consumption of the SRAM cell structure in the select state, Iread represents the read current of the SRAM cell structure, Twl represents the duration during which the wordline is at a high level during the read operation, and f represents frequency.
Half Select: For a discharge path within a certain time, the power consumption can be expressed by the following formula (4):Phalf=Ipre·Twl·Vdd·f  (4)
In the formula (4), Phalf represents the power consumption of the SRAM cell structure in the selecting state, and Ipre represents the precharged current of the SRAM cell structure.
Static: The power consumption is determined by the leakage (Leakage).
Twl is determined by the required voltage difference ΔVBL of the desired bit line, and can be expressed by the following formula (5):
                              T          WL                =                                                            C                BL                            ·                                                          ⁢              Δ                        ⁢                                                  ⁢                          V              BL                                            I            read                                              (        5        )            
In formula (5), ΔVBL represents the voltage difference of the bit line, that is the difference between the voltages of the same bit line before and after being read.
It can be known from the formulas (3)-(5) that, the operational power consumption of the SRAM cell can be reduced by reducing Twl, which can be realized by increasing the discharge speed of the bit line. Therefore, it has become a research subject of the present invention that how to dynamically adjust Twl through change of the operational address of the dual ports, and finally reduce the operational power consumption of the SRAM cell.